BSD Compiler V-2023.12

    BSD Compiler is an automated tool for the synthesis and verification of boundary scan logic in ASICs and ICs within the Design Compiler synthesis environment. It synthesizes boundary scan from user's RTL description utilizing DesignWare JTAG components. After synthesis, a compliance checker in the tool verifies the boundary scan logic for compliance to the IEEE 1149.1 standard. The tool automatically creates a boundary scan description language (BSDL) file for board-level test and generates functional and DC parametric vectors for manufacturing test.

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