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Partner Certification & Solutions Catalog

SYNOPSYS

Products

3DIC Compiler

Synopsys 3DIC Compiler is designed for advanced multi-die and 3D chip designs, offering a unified platform that integrates exploration, routing, analysis, and verification processes.

  • Platform SLES 15
  • Hardware Architecture x86-64
  • Highlights

Avalon

Avalon, which is a CAD navigation and debug tool used for failure analysis and design debugging. Avalon enables detailed failure analysis with cross-mapping across various design domains and integrates seamlessly with legacy databases like Camelot™ and Merlin™.

  • Platform SLES 15, SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

BSD Compiler

BSD Compiler is an automated tool for the synthesis and verification of boundary scan logic in ASICs and ICs within the Design Compiler synthesis environment. It synthesizes boundary scan from user's RTL description utilizing DesignWare JTAG components. After synthesis, a compliance checker in the tool verifies the boundary scan logic for compliance to the IEEE 1149.1 standard. The tool automatically creates a boundary scan description language (BSDL) file for board-level test and generates functional and DC parametric vectors for manufacturing test.

  • Platform SLES 15, SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

CATS

CATS is the most advanced and full featured mask data preparation (MDP) software available for semiconductor photomask manufacturing. This powerful and flexible solution is the standard for data fracturing, photomask inspection and metrology. Providing state-of-the-art data compression algorithms, scalable distributed processing, hierarchical and flat fracturing, and output for all mask writer formats, CATS is the industry’s best performing, most trusted MDP solution.

  • Platform SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

Certify

Verification is the most time consuming task in ASIC design today. The Certify ASIC RTL prototyping software from Synopsys helps to accelerate the verification phase by allowing you to build multi-FPGA based prototypes of ASIC designs in an easy, intuitive fashion, with no modifications to the original design. Certify is being used successfully at hundreds of sites and is a user-friendly tool that works directly from your RTL code. Certify is tightly integrated with the other hardware and software tools that make up the Confirma rapid prototyping platform. Certify Highlights Easy-to-use graphical user interface flow guide Automatic and manual partitioning Automates tasks such as gated-clock conversion, I/O pin multiplexing and signal-to-trace assignments Uses Synopsys design constraints to manage timing Tightly integrated with Confirma flow hardware Supports multi-core parallel processing for faster runtimes Supports most leading FPGA devices Industry standard Synplify Premier synthesis engine included

  • Platform SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

Certitude

The Certitude Functional Qualification System is the only solution that objectively measures the overall effectiveness of your verification environment. It identifies verification weaknesses that allow bugs to go undetected and lead to functional problems, silicon re-spins, and delays to market. For designs targeting automotive, Certitude assesses safety mechanisms as required by the ISO 26262 standard. The Certitude system does this with unique automation technology that provides quick feedback on the most serious problems and supports the efficient analysis and correction of problems.

  • Platform SLES 15, SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

CosmosScope

Today's complex integrated circuit (IC) designs generate a vast amount of simulation data. CosmosScope™ turns that mountain of data into useful information. With powerful analysis and measurement capabilities, patented waveform-calculator technology, and scripting language based on the industry standard Tcl/Tk, CosmosScope offers unparalleled capability and flexibility to analyze design performance and ensure design quality. CosmosScope supports all Synopsys simulators: HSPICE®, NanoSim™, Saber® and SaberHDL. CosmosScope benefits Supports all Synopsys simulation products with a single viewer including HSPICE, NanoSim Saber, and SaberHDL Provides powerful Tcl/Tk-based scripting language for easy customization Performs post-processing of analog and digital simulation results Automatically annotates graphs with design information using true WYSIWYG graphics, including arrows, shapes and text Annotates graphs with 50 types of measurements for immediate visual feedback on design performance Saves and restores graphs for further editing—entire CosmosScope sessions can be saved and restored to pick up where you left off Streamlines the design process through tight integration with Synopsys' Cosmos full-custom design environment and third-party design frameworks

  • Platform SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

Coverity Connect

Coverity Connect is part of the Coverity Static Analysis suite, which is a tool designed to detect and manage software defects, security vulnerabilities, and quality issues early in the development cycle. It offers static code analysis (SAST), which scans source code without executing it, to identify critical bugs and vulnerabilities. Coverity Connect is the web-based interface for managing and reviewing the issues found during code analysis.

  • Platform SLES 15
  • Hardware Architecture x86-64
  • Highlights

Custom Compiler

Custom Compiler is Synopsys' full-custom solution that features the pioneering visually-assisted automation flow that speeds up custom design tasks, reduces iterations and enables reuse. Tuned for rapid implementation of FinFET custom designs, it shortens the time it takes to complete FinFET custom design tasks from days to hours. Its visually-assisted automation flow leverages the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. The visually-assisted automation flow in Custom Compiler is based on four types of Assistants: Layout, In-Design, Template and Co-Design. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup and the intuitive menu structure ensures a minimal learning curve for experienced layout engineers. Custom Compiler provides an open environment spanning schematic, simulation analysis and layout. Unified with Synopsys' circuit simulation, physical verification and digital implementation tools, Custom Compiler provides a comprehensive custom design solution.

  • Platform SLES 15, SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

Custom Infrastructure

Synopsys Custom Infrastructure is part of the broader Custom Design Family. It is used within Synopsys' analog and mixed-signal design solutions, including tools like the Custom Compiler. It integrates with various Synopsys and third-party tools, offering a flexible base for custom IC design and verification.

  • Platform SLES 15
  • Hardware Architecture x86-64
  • Highlights

CustomSim

The CustomSim FastSPICE simulator delivers superior verification performance and capacity for all classes of design, including, custom digital, memory and analog/mixed-signal circuits. The comprehensive offering includes advanced analysis options for native circuit checking, power, signal and MOS reliability analysis and mixed-signal simulation. CustomSim, in combination with the CustomExplorer Ultra advanced regression and analysis environment, provides a complete mixed-signal verification solution that boosts productivity.

  • Platform SLES 15, SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

Custom WaveView

Custom WaveView is a full analog and mixed-signal display and analysis environment, reading simulation results from either analog or digital simulators and allowing complete conversion between views. For instance, Custom WaveView can read-in the analog results of an HSPICE ® simulation, convert those waveforms to digital (single or multi-bit with user-selectable thresholds) and export those results for use in a digital simulation. Custom WaveView also provides a host of capabilities for displaying, measuring, manipulating and saving simulation results. In addition to multiple panels containing waveforms, Custom WaveView can also display more than one waveform tab allowing the designer to mix-and-match time and frequency domains in a single session.

  • Platform SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

Custom WaveView ADV

Custom WaveView ADV is a netlist-based debugging environment for SPICE and FastSPICE simulators such as HSPICE, FineSim and CustomSim. Custom WaveView ADV is also tightly integrated with Custom WaveView, enabling waveform cross-probing. Together, these tools aid designers in rapidly performing customized advanced analyses in a highly-productive design debugging and waveform analysis environment.

  • Platform SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

DC Explorer

DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerating design implementation. With tolerance to incomplete design data, 5-10X faster runtimes and 10% timing and area correlation to DC Ultra (Topographical), it provides early visibility into implementation results. DC Explorer enables designers to efficiently perform what-if analyses of various design configurations early in the design cycle to speed the development of high quality RTL and constraints and drive a faster, more convergent design flow. It also generates an early netlist that can be used to begin physical exploration in IC Compiler. With push-button access to IC Compiler design planning from inside the RTL exploration environment, DC Explorer lets designers easily create and modify floorplans very early in the design cycle.

  • Platform SLES 15, SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

Design Compiler (Synthesis)

Design Compiler in the Galaxy Design Platform is the industry's most comprehensive and production-proven suite of RTL synthesis and test solutions. Its premier synthesis product, DC Ultra, shares topographical technology with the IC Compiler physical implementation solution to enable designers to accurately predict post-layout timing, power and area during RTL synthesis without the need for wireload model-based timing approximations. The tight correlation between synthesis and physical implementation significantly reduces costly and time-consuming design iterations.

  • Platform SLES 15, SLES 12, SLES 11
  • Hardware Architecture x86-64, x86
  • Highlights

Design Compiler Graphical

Continuing the trend of delivering innovative synthesis technology, Design Compiler Graphical delivers superior quality of results and streamlines the flow for a faster, more predictable design implementation. Design Compiler Graphical uses advanced optimizations combined with accurate net delay modeling to achieve 5% faster timing post-placement. It extends DC Ultra topographical technology to provide physical guidance to IC Compiler, tightening timing and area correlation between synthesis and placement to 5% while speeding-up IC Compiler placement by 1.5X.

  • Platform SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

Design Vision (Synthesis)

Design Vision is a graphical user interface (GUI) provided by Synopsys to enable engineers to perform logic synthesis and design analysis using the Design Compiler. It allows for easy visualization of RTL designs, constraints, and synthesis results, facilitating better interaction and understanding of the synthesis process. Users can work with various representations of the design, such as schematics or netlists, and access features like timing analysis and power optimization directly through this interface.

  • Platform SLES 15
  • Hardware Architecture x86-64
  • Highlights

DesignWare Developer (Synthesis)

DesignWare Developer is part of the DesignWare family, offering a collection of IP libraries used for building complex SoC (System-on-Chip) designs. It provides synthesizable IP for components like datapaths, memory controllers, and AMBA microcontrollers, enabling faster development cycles by offering pre-built, silicon-proven IP blocks. These components are crucial for optimizing performance, reducing design risk, and accelerating time to market.

  • Platform SLES 15
  • Hardware Architecture x86-64
  • Highlights

DesignWare IP Virtualizer Development Kits

Synopsys DesignWare IP Virtualizer Development Kits are software development kits (SDKs) that use a virtual prototype to enable developers to quickly bring-up, debug, and test software for DesignWare IP in parallel with SoC development.

  • Platform SLES 12, SLES 11
  • Hardware Architecture x86-64
  • Highlights

DFD

DFD (Design For Debug), which is part of Synopsys' DesignWare offering, is a methodology used to facilitate the debug process in ASIC and SoC designs. It provides features that enhance the ability to observe and control the internal state of a chip during its post-silicon validation phase, ensuring faster debugging and testing cycles.

  • Platform SLES 15
  • Hardware Architecture x86-64
  • Highlights