DC Explorer V-2023.12

DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerating design implementation. With tolerance to incomplete design data, 5-10X faster runtimes and 10% timing and area correlation to DC Ultra (Topographical), it provides early visibility into implementation results. DC Explorer enables designers to efficiently perform what-if analyses of various design configurations early in the design cycle to speed the development of high quality RTL and constraints and drive a faster, more convergent design flow. It also generates an early netlist that can be used to begin physical exploration in IC Compiler. With push-button access to IC Compiler design planning from inside the RTL exploration environment, DC Explorer lets designers easily create and modify floorplans very early in the design cycle.

DC Explorer, which is part of Synopsys' Design Compiler family, is supported on SUSE Linux Enterprise Server (SLES) 15.

• Category Engineering
• Highlights

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