Design Compiler Graphical L-2016.03

Continuing the trend of delivering innovative synthesis technology, Design Compiler Graphical delivers superior quality of results and streamlines the flow for a faster, more predictable design implementation. Design Compiler Graphical uses advanced optimizations combined with accurate net delay modeling to achieve 5% faster timing post-placement. It extends DC Ultra topographical technology to provide physical guidance to IC Compiler, tightening timing and area correlation between synthesis and placement to 5% while speeding-up IC Compiler placement by 1.5X.

• Category High Performance Scientific/Technical Computing (HPC), Other Development and Deployment
• Highlights

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