Security vulnerability: L1D data cache eviction and Vector Register sampling - CVE-2020-0548, CVE-2020-0549
This document (000019635) is provided subject to the disclaimer at the end of this document.
SUSE Linux Enterprise Server 12
Observers running code can find out about modified cache line data on the same CPU core, either in their own thread or in another hyperthread on the same core.
Observers running code can find out about higher order bits of vector registers, used recently or in another hyperthread on the same core. The disclosure is done using methods described in the MDS attacks.
If all mitigations for TAA and MDS were already previously applied, the impact of these new issues is low.
The Intel Security Advisory for this issue can be found here :
Additionaly required for mitigating these two new attacks are Intel CPU Microcode updates for the affected CPUs.
These new CPU Microcode updates will likely be delivered by Intel in June 2020.
No additional Linux Kernel or other software related fixes will be needed.
SUSE TID 7023736 for Microarchitectural Data Sampling attacks
SUSE Blog for TSX Asynchronous Abort attacks
SUSE TID 7024251 for TSX Asynchronous Abort attacks
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- Document ID:000019635
- Creation Date: 28-May-2020
- Modified Date:28-May-2020
- SUSE Linux Enterprise Server
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