Security vulnerability: L1D data cache eviction and Vector Register sampling - CVE-2020-0548, CVE-2020-0549

This document (000019635) is provided subject to the disclaimer at the end of this document.

Environment

SUSE Linux Enterprise Server 15
SUSE Linux Enterprise Server 12

Situation

Security researchers have identified two new Intel CPU sidechannel attacks, similar to the MDS (Multiarchitectural Data Sampling) and TAA (TSX Asynchronous Abort) attacks.
 
1.  L1D Data Cache Eviction sampling

Observers running code can find out about modified cache line data on the same CPU core, either in their own thread or in another hyperthread on the same core.
 
2. Vector Register sampling

Observers running code can find out about higher order bits of vector registers, used recently or in another hyperthread on the same core. The disclosure is done using methods described in the MDS attacks.

If all mitigations for TAA and MDS were already previously applied, the impact of these new issues is low.

The Intel Security Advisory for this issue can be found here : 
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html

Resolution

Mitigations for both attacks are the same as described for the MDS and TAA attacks.

Additionaly required for mitigating these two new attacks are Intel CPU Microcode updates for the affected CPUs.

These new CPU Microcode updates will likely be delivered by Intel in June 2020.
No additional Linux Kernel or other software related fixes will be needed.

Cause

Status

Security Alert

Additional Information

Disclaimer

This Support Knowledgebase provides a valuable tool for SUSE customers and parties interested in our products and solutions to acquire information, ideas and learn from one another. Materials are provided for informational, personal or non-commercial use within your organization and are presented "AS IS" WITHOUT WARRANTY OF ANY KIND.

  • Document ID:000019635
  • Creation Date: 28-May-2020
  • Modified Date:28-May-2020
    • SUSE Linux Enterprise Server

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