Security vulnerability: Microarchitectural Store Buffer Data Sampling (MSBDS) aka CVE-2018-12126, CVE-2018-12127,CVE-2018-12130, CVE-2019-11091
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SUSE Linux Enterprise Server 12
SUSE Linux Enterprise Server 11
The issues identified above share the same mitigations : a combination of CPU Microcode updates, and Kernel and VMM mitigations via software updates.
- The Intel CPU instruction called "VERW" is enhanced by the new CPU Microcode such that it flushes all buffers and ports. The VERW instruction will be called during task switch or VM switch by the patched kernels and hypervisors.
- Disabling Hyper Threading to avoid cross CPU thread information leakage. (Note : This is recommended in high security scenarios).
mds=offThe mitigation is fully disabled.
mds=fullEnables the mitigation on vulnerable CPUs.(Note: This is the SUSE default if the option is not given.)
mds=full,nosmtEnables the mitigations on vulnerable CPUs, and also disables HyperThreading.
Not affectedThe processor is not affected by these issues.
There is no mitigation enabled for this issue.
Vulnerable: Clear CPU buffers attempted, no microcodeNo microcode is not present that the kernel can use.
Mitigation: Clear CPU buffersThe microcode is present and used to clear CPU buffers.
SMT: vulnerableSMT is enabled and the CPU is affected by the Load Port and Fill Buffer issues.
SMT: disabledSMT is disabled and so not affected by cross thread information leakage.
SMT Host state unknownKernel runs in a VM, and the Host SMT state is unknown
SMT: mitigatedThis will be displayed if the CPU is only affected by the Store Buffer issue (CVE-2018-12126), and the mitigation is enabled.
If the option is not present, the mitigation is enabled by default,depending if the CPU model is affectedmds=onThe mitigation is force enabled.
mds=offThe mitigation is force disabled.
smt=offThe mitigation is force disabled.
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- Document ID:7023881
- Creation Date: 14-May-2019
- Modified Date:03-Mar-2020
- SUSE Linux Enterprise Server
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